The present invention relates to a semiconductor device and a method for forming the same, more particularly, to a semiconductor device which can easily control the overlap of a buried gate and a junction region and a method of manufacture thereof.
Recently, many electronic appliances are equipped with semiconductor devices. The semiconductor device includes electronic elements such as a transistor, a resistor and a capacitor. These electronic elements are integrated on a semiconductor substrate, after being designed to perform a partial function of the electronic products. For instance, electronic products e.g., a computer or a digital camera includes electronic devices such as a memory chip for data storage and a processing chip for the information control, and the memory chip and the processing chip includes electronic elements integrated on the semiconductor substrate.
With the increasing demand for electronic devices, semiconductor devices need to be highly integrated to satisfy the consumer needs for excellent performance and low price. As the integration density of semiconductor memory devices increases, the design rule is reduced and the patterns of the semiconductor device is made more dense. As the fine features and high integration of the semiconductor device are progressed, the chip area is increased proportionally to the memory capacity, but the cell area in which the patterns of the semiconductor device is formed is reduced. Accordingly, as more patterns have to be formed within a restricted cell area so as to secure a desired memory capacity, a micro-pattern in which the critical dimension of pattern is reduced needs to be formed.
Methods for forming a micro-pattern includes a method of using a phase shift mask as a photo mask, a Contrast Enhancement Layer (CEL) method for forming a separate thin film for improving image contrast on a wafer, a Tri Layer Resister (TLR) method of interposing an intermediate layer such as Spin On Glass (SOG) between photosensitive films of two layers, and a silylation method of selectively doping a silicon in the upper portion of the photosensitive film have been developed to lower the resolution threshold.
In the meantime, since the channel length becomes short as the semiconductor device becomes highly integrated, high concentration doping of the channel is unavoidable so as to secure the characteristics of a transistor. Thus, the deterioration of refresh characteristics needs to be continuously solved. For this, a gate structure or a recess gate structure is transformed into a buried gate structure so that a gate is formed at the lower portion of the bit line. Accordingly, the capacitance between the gate and the bit line and the total capacitance of a bit line can be reduced.
Generally, in the buried gate, an etch back process is performed in a gate metal so that the gate metal of a given thickness remains within a trench. This is done after the semiconductor substrate is deeply etched with a given depth to form the trench and the gate metal is formed on the whole upper portion to fill the trench. Here, the variation of the etch-backed depth exists in the etch back process. Like this, in case the etch-backed depth is not uniform and the thickness of the electrode of the gate is decreased, the gap between the gate electrode and the junction region formed in the active area is widened, so that the channel resistance is increased. Accordingly, there is a problem in that the characteristic of the semiconductor device is deteriorated.